Tao: Re-Thinking DL-based Microarchitecture Simulation
Santosh Pandey Amir Yazdanbakhsh Hang Liu
Microarchitecture simulators are indispensable tools for microarchitecture
designers to validate, estimate, and optimize new hardware that meets specific
design requirements. While the quest for a fast, accurate and detailed
microarchitecture simulation has been ongoing for decades, existing simulators
excel and fall short at different aspects: (i) Although execution-driven
simulation is accurate and detailed, it is extremely slow and requires
expert-level experience to design. (ii) Trace-driven simulation reuses the
execution traces in pursuit of fast simulation but faces accuracy concerns and
fails to achieve significant speedup. (iii) Emerging deep learning (DL)-based
simulations are remarkably fast and have acceptable accuracy but fail to
provide adequate low-level microarchitectural performance metrics crucial for
microarchitectural bottleneck analysis. Additionally, they introduce
substantial overheads from trace regeneration and model re-training when
simulating a new microarchitecture.
  Re-thinking the advantages and limitations of the aforementioned simulation
paradigms, this paper introduces TAO that redesigns the DL-based simulation
with three primary contributions: First, we propose a new training dataset
design such that the subsequent simulation only needs functional trace as
inputs, which can be rapidly generated and reused across microarchitectures.
Second, we redesign the input features and the DL model using self-attention to
support predicting various performance metrics. Third, we propose techniques to
train a microarchitecture agnostic embedding layer that enables fast transfer
learning between different microarchitectural configurations and reduces the
re-training overhead of conventional DL-based simulators. Our extensive
evaluation shows {\ours} can reduce the overall training and simulation time by
18.06x over the state-of-the-art DL-based endeavors.