Accelerating local laplacian filters on FPGAs
Shashwat Khandelwal Ziaul Choudhury Shashwat Shrivastava Suresh Purini
Images when processed using various enhancement techniques often lead to edge
degradation and other unwanted artifacts such as halos. These artifacts pose a
major problem for photographic applications where they can denude the quality
of an image. There is a plethora of edge-aware techniques proposed in the field
of image processing. However, these require the application of complex
optimization or post-processing methods. Local Laplacian Filtering is an
edge-aware image processing technique that involves the construction of simple
Gaussian and Laplacian pyramids. This technique can be successfully applied for
detail smoothing, detail enhancement, tone mapping and inverse tone mapping of
an image while keeping it artifact-free. The problem though with this approach
is that it is computationally expensive. Hence, parallelization schemes using
multi-core CPUs and GPUs have been proposed. As is well known, they are not
power-efficient, and a well-designed hardware architecture on an FPGA can do
better on the performance per watt metric. In this paper, we propose a hardware
accelerator, which exploits fully the available parallelism in the Local
Laplacian Filtering algorithm, while minimizing the utilization of on-chip FPGA
resources. On Virtex-7 FPGA, we obtain a 7.5x speed-up to process a 1 MB image
when compared to an optimized baseline CPU implementation. To the best of our
knowledge, we are not aware of any other hardware accelerators proposed in the
research literature for the Local Laplacian Filtering problem.