When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural
  Networks on FPGA
Hongxiang Fan Hao Chen Liam Castelli Zhiqiang Que He Li Kenneth Long Wayne Luk
Bayesian Neural Networks (BayesNNs) have demonstrated their capability of
providing calibrated prediction for safety-critical applications such as
medical imaging and autonomous driving. However, the high algorithmic
complexity and the poor hardware performance of BayesNNs hinder their
deployment in real-life applications. To bridge this gap, this paper proposes a
novel multi-exit Monte-Carlo Dropout (MCD)-based BayesNN that achieves
well-calibrated predictions with low algorithmic complexity. To further reduce
the barrier to adopting BayesNNs, we propose a transformation framework that
can generate FPGA-based accelerators for multi-exit MCD-based BayesNNs. Several
novel optimization techniques are introduced to improve hardware performance.
Our experiments demonstrate that our auto-generated accelerator achieves higher
energy efficiency than CPU, GPU, and other state-of-the-art hardware
implementations.