SAFFIRA: a Framework for Assessing the Reliability of
  Systolic-Array-Based DNN Accelerators
Mahdi Taheri Masoud Daneshtalab Jaan Raik Maksim Jenihhin Salvatore Pappalardo Paul Jimenez Bastien Deveautour Alberto Bosio
Systolic array has emerged as a prominent architecture for Deep Neural
Network (DNN) hardware accelerators, providing high-throughput and low-latency
performance essential for deploying DNNs across diverse applications. However,
when used in safety-critical applications, reliability assessment is mandatory
to guarantee the correct behavior of DNN accelerators. While fault injection
stands out as a well-established practical and robust method for reliability
assessment, it is still a very time-consuming process. This paper addresses the
time efficiency issue by introducing a novel hierarchical software-based
hardware-aware fault injection strategy tailored for systolic array-based DNN
accelerators.