Exploring Hardware Friendly Bottleneck Architecture in CNN for Embedded
  Computing Systems
Xing Lei Longjun Liu Zhiheng Zhou Hongbin Sun Nanning Zheng
In this paper, we explore how to design lightweight CNN architecture for
embedded computing systems. We propose L-Mobilenet model for ZYNQ based
hardware platform. L-Mobilenet can adapt well to the hardware computing and
accelerating, and its network structure is inspired by the state-of-the-art
work of Inception-ResnetV1 and MobilenetV2, which can effectively reduce
parameters and delay while maintaining the accuracy of inference. We deploy our
L-Mobilenet model to ZYNQ embedded platform for fully evaluating the
performance of our design. By measuring in cifar10 and cifar100 datasets,
L-Mobilenet model is able to gain 3x speed up and 3.7x fewer parameters than
MobileNetV2 while maintaining a similar accuracy. It also can obtain 2x speed
up and 1.5x fewer parameters than ShufflenetV2 while maintaining the same
accuracy. Experiments show that our network model can obtain better performance
because of the special considerations for hardware accelerating and
software-hardware co-design strategies in our L-Mobilenet bottleneck
architecture.