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sirus
's Collections
RTL
TS
video generation
code
AI gofasters
scripting
uncensoring
interesting
RTL
updated
Mar 26
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bnadimi/PyraNet-Verilog
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Feb 10
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692k
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458
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13
JayZhang1/Verilogdata4pretrainCODET5
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Apr 9, 2023
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256k
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270
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wangxinze/Verilog_data
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Nov 14, 2023
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187k
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53
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SamShrubo/F24-FFH-Verilog
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Nov 20, 2024
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175k
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16
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shailja/Verilog_GitHub
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Sep 20, 2023
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243
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dcmberdani/childai_verilog_bigquery_dataset_processed
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Mar 15, 2024
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171k
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3
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ajn313/verilog_dataset
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Feb 25, 2024
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109k
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Cashio70/vhdl-clean
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May 3, 2024
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rtl-llm/vhdl_github
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Feb 25
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