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Given the following text description, write Python code to implement the functionality described below step by step
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Description:
 Ripple Counter from Toggle Flip-Flops
In this example we create a ripple counter from toggle flip-flops. 
We also show how to define new Magma Circuits
and introduce generators.
Step1:  In the last example, we defined a function that created a
toggle flip-flop (TFF) from a DFF and an XOR gate.
Let's convert the TFF to a Circuit. 
In Magma a Circuit is equivalent to a verilog module.
Circuits can be instanced and then wired to other circuits.
m.ClockIO() appends Magma's standard clock interface ports to the interface. When no parameters are specified, this just adds the port CLK with type In(Clock).
Step2:  Let's inspect the interface to see the result of appending m.ClockIO().
Step3:  Now we'll define a generator for our RippleCounter that accepts a single argument width. A generator in magma is a subclass of m.Generator that defines a static method generate which returns Magma Circuit.
Step4:  Now we can generate a 4-bit RippleCounter by calling the generate function directly.
Step5:  Let's test our circuit using fault.  Magma's Python simulator does not support asynchronous logic, so we'll use verilator.
Step6:  We can also look at the generated verilog
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Python Code:
import magma as m
Explanation: Ripple Counter from Toggle Flip-Flops
In this example we create a ripple counter from toggle flip-flops. 
We also show how to define new Magma Circuits
and introduce generators.
End of explanation
from mantle import DFF
class TFF(m.Circuit):
    io = m.IO(O=m.Out(m.Bit)) + m.ClockIO()
    ff = DFF()
    m.wire( ff(~ff.O), io.O )
Explanation: In the last example, we defined a function that created a
toggle flip-flop (TFF) from a DFF and an XOR gate.
Let's convert the TFF to a Circuit. 
In Magma a Circuit is equivalent to a verilog module.
Circuits can be instanced and then wired to other circuits.
m.ClockIO() appends Magma's standard clock interface ports to the interface. When no parameters are specified, this just adds the port CLK with type In(Clock).
End of explanation
print(TFF)
Explanation: Let's inspect the interface to see the result of appending m.ClockIO().
End of explanation
class RippleCounter(m.Generator):
    @staticmethod
    def generate(width: int):
        class _RippleCounter(m.Circuit):
            name = f'Ripple{width}'
            io = m.IO(O=m.Out(m.Bits[width])) + m.ClockIO()
            tffs = [TFF(name=f"tff{i}") for i in range(width)]
            O = io.CLK
            for i in range(width):
                m.wire(m.clock(O), tffs[i].CLK)
                O = tffs[i].O
                m.wire(O, io.O[i])
        return _RippleCounter
Explanation: Now we'll define a generator for our RippleCounter that accepts a single argument width. A generator in magma is a subclass of m.Generator that defines a static method generate which returns Magma Circuit.
End of explanation
Ripple4 = RippleCounter.generate(4)
print(repr(Ripple4))
Explanation: Now we can generate a 4-bit RippleCounter by calling the generate function directly.
End of explanation
import fault
tester = fault.Tester(Ripple4, Ripple4.CLK)
for i in range(1 << 4):
    tester.step(2)
    tester.print("O=%x\n", Ripple4.O)
tester.compile_and_run(target="verilator", disp_type="realtime")
Explanation: Let's test our circuit using fault.  Magma's Python simulator does not support asynchronous logic, so we'll use verilator.
End of explanation
m.compile("build/ripple", Ripple4, inline=True)
%%bash
cat build/ripple.v
Explanation: We can also look at the generated verilog
End of explanation
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