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Given the following text description, write Python code to implement the functionality described below step by step
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Description:
 https
Step2:  IP  ClockDivider
Non SoC Test
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Python Code:
#This notebook also uses the `(some) LaTeX environments for Jupyter`
#https://github.com/ProfFan/latex_envs wich is part of the
#jupyter_contrib_nbextensions package
from myhdl import *
from myhdlpeek import Peeker
import numpy as np
import pandas as pd
import matplotlib.pyplot as plt
%matplotlib inline
from sympy import *
init_printing()
import itertools
from IPython.display import clear_output
#https://github.com/jrjohansson/version_information
%load_ext version_information
%version_information myhdl, myhdlpeek, numpy, pandas, matplotlib, sympy, itertools, IPython
#helper  functions to read in the .v and .vhd generated files into python
def VerilogTextReader(loc, printresult=True):
    with open(f'{loc}.v', 'r') as vText:
        VerilogText=vText.read()
    if printresult:
        print(f'***Verilog modual from {loc}.v***\n\n', VerilogText)
    return VerilogText
def VHDLTextReader(loc, printresult=True):
    with open(f'{loc}.vhd', 'r') as vText:
        VerilogText=vText.read()
    if printresult:
        print(f'***VHDL modual from {loc}.vhd***\n\n', VerilogText)
    return VerilogText
def ConstraintXDCTextReader(loc, printresult=True):
    with open(f'{loc}.xdc', 'r') as xdcText:
        ConstraintText=xdcText.read()
    if printresult:
        print(f'***Constraint file from {loc}.xdc***\n\n', ConstraintText)
    return ConstraintText
Explanation: https://yangtavares.com/2017/07/31/creating-a-simple-overlay-for-pynq-z1-board-from-vivado-hlx/
End of explanation
@block
def ClockDivider(Divisor, clkOut, clk,rst):
    
    Simple Clock Divider based on the Digilint Clock Divider
    https://learn.digilentinc.com/Documents/262
    
    Input:
        Divisor(32 bit): the clock frequncy divide by value
        clk(bool): The input clock
        rst(bool): clockDivider Reset
    
    Ouput:
        clkOut(bool): the divided clock ouput
        count(32bit): the value of the internal counter
    
    
    count_i=Signal(modbv(0)[32:])
    @always(clk.posedge, rst.posedge)
    def counter():
        if rst:
            count_i.next=0
        elif count_i==(Divisor-1):
            count_i.next=0
        else:
            count_i.next=count_i+1
    
    clkOut_i=Signal(bool(0))
    @always(clk.posedge, rst.posedge)
    def clockTick():
        if rst:
            clkOut_i.next=0
        elif count_i==(Divisor-1):
            clkOut_i.next=not clkOut_i
        else:
            clkOut_i.next=clkOut_i
        
        
    
    @always_comb
    def OuputBuffer():
        clkOut.next=clkOut_i
       
    return instances()
            
        
RefClkFreq=125e6
TargetClkFreq=40
DivsionFactor=int(RefClkFreq/TargetClkFreq)
DivsionFactor
Peeker.clear()
clk=Signal(bool(0)); Peeker(clk, 'clk')
Divisor=Signal(intbv(DivsionFactor)[32:]); Peeker(Divisor, 'Divisor')
clkOut=Signal(bool(0)); Peeker(clkOut, 'clkOut')
rst=Signal(bool(0)); Peeker(rst, 'rst')
DUT=ClockDivider(Divisor, clkOut, clk,rst)
DUT.convert()
VerilogTextReader('ClockDivider');
ConstraintXDCTextReader('ClockAXI');
Explanation: IP  ClockDivider
Non SoC Test
End of explanation
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