AN8080 - Using a Discrete Crystal as a PLD Clock Source

Using a Discrete Crystal as a
PLD Clock Source
June 2009
Application Note AN8080
Clocks are a necessary part of synchronous PLD designs (e.g. Lattice Semiconductor’s ispMACH® 4000ZE and
MachXO™). Designers will typically use integrated oscillators but there are other, less expensive options. This document will discuss the generation of a clock signal using an inexpensive crystal circuit to minimize board costs.
The Crystal Oscillator Circuit
Discrete crystals are two terminal passive devices that are made from a piezoelectric material. Circuits that use
crystals as part of the feedback path are known as crystal oscillator circuits. Crystal oscillator circuits oscillate at a
specific frequency that is based upon the mechanical resonance of the crystal device. Figure 1 shows an example
of a crystal device (a), the crystal schematic symbol (b), and the electrical equivalent of a crystal (c).
Figure 1. Crystal (a) Device, (b) Symbol, (c) Electrical Equivalent
Crystals are specified to operate at a given frequency and in a given mode. The basic mode of operation is referred
to as the fundamental mode and is available in frequencies that range from about 30kHz to 50MHz. To obtain
higher frequencies a crystal is specified to operate in a 3rd or 5th overtone mode which is close in frequency to the
3rd and 5th harmonic of the fundamental frequency (operating at exact multiples is less stable because, the crystal
will prefer the fundamental mode). Overtone crystal oscillator circuits are significantly more complex, more sensitive to component variations, and not recommended for use with a PLD. Therefore, the first step in designing a
crystal oscillator with a PLD is to select a crystal with the desired fundamental frequency.
To operate a crystal at the fundamental frequency, the Pierce circuit can be realized using an inverter inside a PLD
combined with some external resistors and capacitors as shown in Figure 2 (a). Typically this type of oscillator circuit is built with a series of three inverters to provide enough phase delay for oscillation to take place. However, this
in not required when using Lattice Semiconductor PLDs. The input buffer and output buffer (not shown) provide
enough delay that a single inverter is all that is needed for the oscillator circuit to function. The two capacitors C1
and C2 are part of the load capacitance (CL) which is specified in the crystal data sheet. The resistor R1 is part of
feedback path while R2 limits the drive power seen by the crystal. Crystal manufactures usually provide documentation with recommended values for the resistors and capacitors.
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Lattice Semiconductor
Using a Discrete Crystal as a PLD Clock Source
Figure 2. Oscillator Circuit using an Inverter within a PLD (a) vs. Integrated Oscillator (b)
To Other Logic
To Other Logic
Comparing Crystal/Pierce Circuit vs. Oscillator
The fundamental advantage of using a discrete crystal as a clock source rather than an integrated oscillator is
lower board cost. The Pierce circuit does, however, require extra passive components, which will slightly increase
design and assembly effort. The tradeoffs are shown in Table 1.
Table 1. Comparing Crystal/Pierce Solution vs. Oscillator
Approximate cost
$0.30 to $0.80
$1.80 to $3.00
Design effort
Pierce circuit must be designed
Minimal / none
Component count
5 (crystal, 2 resistors, 2 capacitors)
4 (oscillator, 1 ferrite, 2 bypass capacitors)
Lab testing
Pierce circuit must be verified
Minimal / none
Frequencies available
~30kHz to 50MHz
1MHz to 250MHz
Pierce Circuit Crystal Components Selection
The first step in designing the Pierce oscillator circuit is selecting the crystal (X1) based upon the required clock frequency supported by the fundamental mode of operation. Further consideration would be given to package size
and parts cost.
The crystal data sheet will specify the load capacitance (CL). The load capacitance is the total capacitance which
will be seen on either side of the crystal. Based on the circuit shown in Figure 2(a), the ideal calculation for (C1)
and (C2) is:
C1 C2
CL =
(C1 + C2)
Where CStray is the stray capacitance around the crystal such as: PLD input and output capacitance, the crystal
mounting pads, mounting pads of the resistors, and PCB trace capacitance (listed in order of significance). In
equation form, this would look like:
Lattice Semiconductor
Using a Discrete Crystal as a PLD Clock Source
In order of significance this equation is broken down as follows: where CPLD_IO_BUFFER is the input and output
capacitance of the PLD buffer. The output capacitance is only included if the value of R2 is near zero ohms. These
values can be found in the PLD manufacturer’s data sheet.
CCRYSTAL_PAD is the capacitance value associated with the PCB mounting pad of the crystal. This capacitance can
be calculated using the following equation where A is the area of the pad (in square inches), d is the thickness of
the board (in inches) between the pad and the ground plane (or power plane, which ever is closer), and is the
dielectric constant of the PCB material. Some typical mounting pad capacitance values are presented in Appendix
CR_PAD is the capacitance value associated with the PCB mounting pads of R1 and R2. This capacitance can be
calculated using the same equation that was used for the crystal mounting pads. Typically the capacitance value for
surface mount 0805 or 0603 devices is significantly less than the capacitance value of either the PLD I/O or the
crystal mounting pad and can be ignored in most cases.
CBOARD_TRACES is the capacitance associated with the traces that connect the crystal to the resistors, capacitors,
and PLD pins. All the components should be placed as close to the PLD as possible for two reasons. First, so that
the trace capacitance value can be estimated to be zero and thus ignored. Secondly, and more importantly, so that
the circuit is protected from surrounding signals that may affect the operation of the crystal oscillator.
The Pierce circuit is fairly robust when using a fundamental mode crystal. As a result, the values of C1 and C2 are
often selected to be the same since this simplifies assembly and reduces inventory costs.
Precautions and Rules of Thumb
When implementing a crystal/Pierce circuit there are some precautions and rules of thumb to be aware of:
• Always select a crystal that is specified to operate in fundamental mode.
• Always refer to the crystal manufacturer data sheets and technical notes to optimize and revise the component
values of the oscillator circuit.
• When laying out the board use routing and Via keepouts to prevent stray signals from running under of near the
crystal circuit which may affect the performance of the oscillator circuit.
• To help isolate the crystal circuit, enclose it with a ground guard ring.
• Place the crystal circuit as close to the PLD as possible to reduce stray capacitance (by minimizing trace
• When assigning pins in the PLD design flow, place XIN and XOUT so that both are as close to the crystal as possible.
• Configure the PLD I/O pull mode to OFF for XIN and XOUT or the circuit may not start.
• Test the circuit across temperature to ensure functionality.
Pulling It All Together
The recommended implementation steps for a proper crystal/PLD Pierce circuit are as follows:
1. Specify PLD pins (XIN, XOUT) based upon the recommended rules of thumb.
2. Select a crystal based upon its fundamental frequency.
Lattice Semiconductor
Using a Discrete Crystal as a PLD Clock Source
3. Design the Pierce circuit per the defined capacitance calculations assuming:
a. C1 = C2
b. Assume CBOARD_TRACES and CR_PAD to be 0pF.
c. Select resistor R1 and R2 values based upon crystal manufacturer recommendations.
d. Check crystal manufacturer datasheets and technical notes for further refinements of the Pierce circuit.
4. Design the board, rigorously following the defined rules of thumb.
5. Lab test the circuit across temperature range to ensure reliable crystal operation. If necessary, revise the
values of C1 and C2 until the Pierce circuit yields desired operation. If CL is too little or too much, the frequency of oscillation may be low or high respectively.
Crystals are a low-cost and accurate clocking alternative that can be used in a number of applications. Crystals are
available in frequencies from 30kHz to 50MHz using the fundamental resonant frequency. A Pierce circuit is recommended for crystal implementation, due to its simplicity, low cost, and robustness. The designer should use the CL
formulas and rules of thumb to specify initial values for C1 and C2 and use bench testing to finalize these values.
Related Literature
• MachXO Family Data Sheet
• ispMACH 4000ZE Family Data Sheet
• Citizen HCM49 data sheet (used on the MachXO Mini Evaluation Board) available on the Citizen Crystal web site
• Citizen crystal design technical note, “Precautions in Oscillation Circuite Design” available on the Citizen Crystal
web site at
• Citizen crystal design technical note, “Reference for Selecting Constants of Oscillation Circuit” available on the
Citizen Crystal web site at
• The ARRL Handbook, available on the AARL web site at
Technical Support Assistance
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e-mail: [email protected]
Revision History
June 2009
Change Summary
Initial release.
Lattice Semiconductor
Using a Discrete Crystal as a PLD Clock Source
Appendix A. Example Calculation
This example calculation is based on the MachXO Mini Evaluation Board. The Citizen HCM49 crystal is available at
25MHz in Fundamental mode. The “Reference for Selecting Constants of Oscillation Circuit” technical note from
Citizen Crystal lists the values as follows:
R1 = 1MΩ
R2 = 1kΩ
C1 = 18pF
C2 = 18pF
CL = 16pF
The dielectric constant for FR4 is about 4.5 and the recommended mounting pads for the HCM49 are 5.5mm by
1.5mm. In a typical 4-layer circuit board, the thickness of the dielectric from the top layer to the ground plane layer
is 0.0115 inches. This results in a crystal mounting pad capacitance of 1.1pF (for each pad). The PLD input capacitance from the MachXO Family Data Sheet is typically 8pF. The PLD output capacitance is ignored as it is isolated
from the crystal by R2. Setting C1 equal to C2 and using the values above results in the following:
16pF =
+ 10.2pF
Solving this equation; we find C = 11.6pF, so we can use a standard value of 12pF for both C1 and C2.
If we now change the design to use a 6-layer circuit board the dielectric thickness drops to 0.0064” (almost half).
This results in the crystal mounting pad capacitance of 2.0pF (almost double) per pad. Solving again, we find that
C = 8pF for both C1 and C2.