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Digital Communications: A Discrete-Time Approach
by Michael Rice

Carrier Phase Synchronization for BPSK Using the Unique Word


In the previous BPSK Simulink Exercise the phase of the unmodulated carrier was assumed known. Unfortunately, this is not the case in practice. The carrier phase is unknown and must be extracted from the received signal using a carrier phase recovery subsystem. In this exercise, you will design a PLL-based carrier phase recovery subsystem for BPSK which will be used to process BPSK modulated data contained in the file bpskcruwdata.mat To deal with the 180-degree phase ambiguity of the PLL-based carrier phase synchronizer, this exercise uses the unique word (UW) method. In the UW method, the symbol decisions are searched for two versions of the UW that correspond to the two possible constellation rotations defined by the phase ambiguity. Once the UW has been found, the phase ambiguity is known and can be corrected.

Textbook References

M-ary QAM: Section 5.3 (pp. 238 - 260), discrete-time realizations: Section 5.3.2 (pp. 256 - 260), partial response pulse shapes: Section A.2 (pp. 676 - 693), discrete-time PLL: Section C.2 (pp. 732 - 747), carrier phase synchronization for BPSK: Section 7.3 (pp. 375 - 381), unique word for phase ambiguity resolution for BPSK: Section 7.7.1 (pp. 396 - 397).


normalized sample rate: 8 samples/bit
normalized carrier frequency: 0.2 cycles/sample
carrier phase: unknown
average energy: 1
pulse shape: SRRC (50% excess bandwidth, span = 12 symbols)
symbol clock offset: 0
input file bpskcruwdata.mat
phase ambiguity resolution unique word: UW = 0 0 0 1 0 1 1 0
input message length: 224 symbols (224 bits or 32 ASCII characters)
the data format is shown below

The packet is repeated 4 times to allow your PLL to acquire and lock.

Design the Detector

Design the detector, shown below, using blocks from the Simulink, DSP System, and Communications System Toolboxes. I recommend you start with the detector from the BPSK Simulink Exercise and make changes as necessary.

Design the loop filter to create a second order loop to the following specifications: closed-loop equivalent noise bandwidth = 0.01 (normalized to the bit rate), damping factor = 0.7071.


  1. For the detector input, use the From File block and set the Filename to bpskcruwdata.mat and set the sample time to 1.

  2. Set the simulation parameters as follows:
    Simulation Time
    Start Time: 0.0
    Stop Time: (12+32*7+8)*8*4-1
    Solver Options
    Type: Fixed-step
    Solver: discrete (no continuous states)
    Fixed step size: auto
    Tasking and sample time options
    Periodic sample time constraint: Unconstrained
    Tasking mode for periodic sample times: SingleTasking

  3. Run the simulation.

  4. The detector produces 976 symbol estimates. Even though the UW and DATA fields are repeated four times, the PLL does not lock until part way through the sample sequence.

  5. To find the data bits, look for the 8-bit UW pattern in the detector output. If you find it, the 224 bits following the UW correspond to 32 7-bit ASCII characters.

  6. If you can't find the 8-bit UW pattern in the detector output, try complementing all the detector outputs and look for the UW in the complemented bit sequence. If you find it, the 224 bits following the UW correspond to 32 7-bit ASCII characters.

  7. Determine the message using either your Matlab script or an ASCII Table.

  8. Plot the phase error (loop filter output) and use this plot to estimate how long (measured in bits) it took your PLL to lock.

  9. Plot the eye diagram and signal space projections.